Electrical apparatus and method for adding binary numbers

ABSTRACT

An electronic binary adder having a plurality of stages, each comprising in combination two logical circuits adapted to perform &#39;&#39;&#39;&#39;COMPARATOR&#39;&#39;&#39;&#39; and &#39;&#39;&#39;&#39;OR EXCLUSIVE&#39;&#39;&#39;&#39; functions and a logical commutator or &#39;&#39;&#39;&#39;IF&#39;&#39;&#39;&#39; switch circuit interconnected to compute the sum of digits of corresponding rank in two binary numbers and the carryover from the summation of the digits of next lower rank in said numbers, and to simultaneously compute also the carryover, if any, to be added to the sum of the digits of next higher rank. Any or each of said logical circuits may comprise a radiationemitting means controlled by signal input and radiationcontrolled signal output means.

United States Patent Inventor Pierre Jo'rgensen Ll-lay-Les-Roses, Seine, France Appl. No. 771,737

Filed Oct. 30, 1968 Patented Oct. 12, 1971 Assignee Compagnie De Saint-Cobain Neuilly-sur-Seine, France Priority Apr. 3, 1964, Apr. 3, 1964, Oct. 30, 1967 France PV969,695, PV969,694 and PV126,291 Continuation-impart of application Ser. No. 444,642, Apr. 1, 1965, now Patent No. 3,348,199, which is a division of application Ser. No. 660,112, Aug. 11,1967, now abandoned.

ELECTRICAL APPARATUS AND METHOD FOR ADDING BINARY NUMBERS 48 Claims, 24 Drawing Figs.

US. Cl 235/176, 307/216, 235/168, 235/175 Int. Cl G061 7/56, G06f 7/50, G06f 7/48 Field of Search 235/168,

Primary Examiner-Eugene G. Botz Assistant Examiner-James F. Gottman AttarneyBauer and Seymour ABSTRACT: An electronic binary adder having a plurality of stages, each comprising in combination two logical circuits adapted to perform COMPARATOR and OR EXCLU- SIVE functions and a logical commutator or 1F" switch circuit interconnected to compute the sum of digits of corresponding rank in two binary numbers and the carryover from the summation of the digits of next lower rank in said numbers, and to simultaneously compute also the carryover, if any, to be added to the sum of the digits of next higher rank. Any or each of said logical circuits may comprise a radiationemitting means controlled by signal input and radiation-controlled signal output means.

( nU bn) U n-1 On bn 2 n =O EXCLUSIVE PATENTEUum 121s?! 3,612,847 .SHEET O3UF 12 FIG. 5

INVENTOR.

mm Jiinmssu AN mms PATENTEUnm 121911 3.612.847

SHEET on HF 12 FIG? FIG. 8

INVENTOR.

BY PIERRE JORCEISEI 5m MW PATENTEDBB 1219" 3,612,847

sum CSBF 12 FIG. 9

- Vb L3 l mvsmoa.

BY PIERRE .IORGEISEI SHEET DBUF 12 PATENTEDUU 121911 FIG. ll

INVEN'IOR.

BY PIERRE JORGEISEI ATT RIEYS PATENTEDu'm 12 IQYI sum 07 0F 12 INVENTOR.

BY PIERRE JORCEISEI Am ATT RIIEYS PATENTEU1111121911 3,612,847

SHEET DSUF 12 FIGQ|7 FIG. I8

102 V50 35 10/. 11K; 1 w MIL. 91 1 a0 99 39 INVENIOR' mm 16mm! AU RIEYS PATENTEUUET 12 an SHEET 1 0 OF 1 2 FIG. I9

FIG. 20

INVENTOR.

mm J11R6EISEII 14 w m mans PATENTEUUET 12 I97! SHEET 1 m 12 3,612,847

FIG.2|

FIG. 22

INVENTOR.

mans Jiincsnsin ELECTRICAL APPARATUS AND METHOD FOR ADDING BINARY NUMBERS This is a continuation-in-part of my application Ser. No. 444,642, filed Apr. 1, 1965 (now U.S. Pat. No. 3,348,199, issued Oct. 17, 1967), Ser. No. 660,1 12, (now abandoned) filed Aug. 1 l, 1967, as a division of said Ser. No. 444,642, and Ser. No. 444,619, filed Apr. 1, 1965 (now abandoned). The disclosures of said prior applications are incorporated herein by reference.

This invention relates to electrical apparatus and more particularly to circuitry adapted, among other things, for use in electronic computers.

One of the objects of the present invention is to provide novel electronic circuitry for automatically computing the sum of binary numbers.

Another object of the invention is to provide a novel com bination of logical comparator and commutator circuits for more rapidly computing the summation of binary numbers.

In order to add two binary numbers A and B, the digits of which having the same rank n will be herein designated by a, and b, respectively, it is necessary to add to the sum of these digits any carryover R, which has resulted from the addition of the digits a and b, of the next lower rank and to obtain the carryover R, resulting from such addition.

Heretofore, this function has been carried out with a relatively complicated combination of logical AND" and OR EXCLUSIVE" circuits in the operation of which there is inherent undesirable delay in the propagation of accurate carryovers. I

It is, therefore, a further object of the invention to provide simplified apparatus for adding binary numbers with greater speed and greater assurance of accuracy than is possible with prior-known apparatus.

Still another object is to provide novel logic comparator and commutator circuitry adapted for use in binary adders or the like whereby absolute separation of a utility or load circuit from a control circuit therefor is achieved.

A still further object is to provide a novel binary adder wherein the carryover resulting from the addition of each column of digits is represented by a voltage and is determined simultaneously with the addition and thus without carryover propagation time.

A still further object is to provide novel simplified logic circuits which make novel use of radiation-emitting and radiation-controlled devices to thereby lower the time constant and hence, the response time thereof as compared to prior-known circuits designed for performing the same and comparable functions.

Still another object is to provide a novel method for electronically performing the addition of binary numbers.

The above and further objects and novel features of the inventionwill more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.

In the drawings, wherein like reference characters refer to structurally or functionally like parts throughout the several views,

FIG. I is a diagrammatic illustration of a single stage of one form of apparatus embodying the invention, the boxes C1 and C2 representing circuits for performing the logic OR EX- CLUSIVE function;

FIG. 2 is a schematic diagram of one specific form of circuitry which may be used in the apparatus of FIGS. 1 and 4;

FIG. 3 is a duplication of FIG. 2 indicating representative values of some of the electrical components;

FIG. 4 is a diagrammatic illustration identical with FIG. 1 with the boxes Cl and C2 representing circuits for performing the logic OR EXCLUSIVE complement function;

FIG. 5 is a diagram similar to FIG. 2 of a modified form of circuitry for a binary adder embodying the invention;

FIG. 6 is a detail diagram of the comparator circuit C] of FIG. 5;

FIG. 7 is a detail diagram of the commutator circuit H of FIG. 5;

FIGS. 8, 9 and 10 are diagrams illustrating modifications or variations of the comparator circuit of FIG. 6;

FIG. 11 is a diagram illustrating a modification or variation of the commutator circuit of FIG. 7;

FIGS. 12, I3 and 14 are diagrams illustrating additional modifications or variations of the comparator circuit of FIG.

FIG. 15 is a duplication of FIG. 14 indicating representative values of electrical components;

FIGS. l6, l7 and 18 are diagrams illustrating further modifications and variations of the comparator circuit of FIG. 6;

FIGS. 19, 20 and 21 are diagrams illustrating further modifications or variations of the commutator circuit of FIG. 7;

FIG. 22 is a duplication of FIG. 21 indicating representative values of electrical components;

FIG. 23 is a diagram of a further modification or variation of the commutator circuit of FIG. 7; and

FIG. 24 is'a diagram illustrating two stages of a parallel binary adding device embodying the invention.

The invention contemplates a novel and greatly simplified electronic binary adder including novel comparator circuits adapted to rapidly and efficiently effect with consistent accuracy and in accordance with a novel method the sum of two binary digits a,, and I2, and a carryover R, represented by voltages indicative of the binary digits 1 and 0 and to also supply the carryover R,, resulting from such summation. In the forms illustrated, by way of example, such adder comprises a plurality of stages, each including two circuits CI and C2 adapted to perform either the logical OR EXCLUSIVE" function (FIG. 1) or the logical OR EXCLUSIVE COMPLEMENT function (FIG. 4) in the performance of binary additions depending upon the convention adopted for representing the binary digits 1 and 0 by different voltages, and a logical commutator circuits H which is capable of connecting its output terminal to one of its two input terminals if a voltage representing the binary digit 1 is applied to its control terminal and capable of connecting its output terminal to its other input terminal if a voltage representing the binary digit 0 is applied to its control terminal. Such a commutator can be designated a logical IF" switch circuit and may be of the construction disclosed in my copending U.S. application Pat. Ser. No. 442,592, filed Mar. 25, I965, now U.S. Pat. No. 3,411,091, and in French Pat. No. 1,398,092. Another suitable form of switch circuit is disclosed in my above-mentioned parent application Ser. No. 444,619.

In the form illustrated in FIGS. 1 to 4, the circuits CI and C2 have signal input terminals 1, 2 and 3, 4 and output terminals 5 and 6, respectively. The switch circuit H comprises the combination of two transistors TI and T2 of the NPN' and PNP" types, respectively, presenting two base terminals inserted between two blocks of N" material and two blocks of P" material, the two base terminals being electrically connected to a control terminal 7 by means of resistors RI and R2 which are preferably of identical values. One of the N blocks of the transistor T1 and one of the P" blocks of the transistor T2 are connected to an output terminal 8, and the remaining blocks-for instance, an emitter and a collector as represented on the drawing-are connected to input terminals 9 and 10.

The switch H is electrically connected with circuits Cl and C2 by connecting input terminals 9 and I0 and control terminal 7 thereof to input terminal 3 of circuit Cl, input terminal 1 of circuit C1 and output terminal 5 of circuit CI, respectively. Output terminal 5 is also connected to input terminal 4 of circuit C2. A resistor R23 having, by way of example, a value of ohms is preferably inserted between input terminals 1 and 10 to prevent short circuiting of the switch H.

In the mode of operation of the adding device as illustrated in FIG. 1 with circuits Cl and C2 performing the logic OR EXCLUSIVE" function, maximum and minimum signal voltages, for example, 4/5 V, and 0, indicative of the binary digits 1 and or the signs and respectively, are applied to the input terminals 1 and 2 to represent the binary digits a,, and b, of rank n in the binary numbers A and B to be added and to the terminals 3 and 9 to represent the carry R,,,, resulting from the addition of the digits of next lower rank nl. In the first stage of an adding device, in which the digits a, and b, of lowest rank are added, the voltage representing the carry R may be supplied by suitable means, such as a circuit G (FIG. 2). In the second and subsequent stages, such voltage representing the carrying R ,,,l is supplied to terminal 9 from terminal 8 of the preceding stage.

The circuit G in the form shown comprises a conductor 20 connected to a source (not shown) of voltage V,,, a resistor R20 connected between said conductor and a switch, the blade 21 of which may be selectively contacted with terminals 22 and 23, and means connecting said terminals to ground through resistors R21 and R22, respectively. Terminal 23 is also connected with an output terminal 25 which may in turn be connected to input terminal 9 of the first stage of the adding device. The values of said resistors are preferably so chosen that the voltages available for application to terminal 25 and hence, to terminal 9, for the two positions of switch blade 21 will be equal to the above-mentioned maximum and minimum voltages chosen to represent the binary digits l and 0.

Thus, under the convention adopted for OR EXCLU- SIVE operation, when blade 21 engages contact 22, the voltage applied to terminal 25 will be 0, which represents R as binary 0, this being the carry introduced into the first stage of the adder when adding the right hand digits, i.e., the digits of lowest rank of two binary numbers.

Based upon the values adopted for resistances R20 and R22 (FIG. 3), when blade 21 engages contact 23 the voltage applied to terminal 25 is equal to 4/5 V,,. In accordance with the above adopted convention, the voltage 4/5 v, represents a carry R, equal to binary 1, this being the carry introduced into the first stage when the device is used for adding binary numbers B andx (A in complement form) as a part of the conventional process for effecting subtraction of A from B.

When voltages are applied to the various terminals as outlined above, the output terminal 5 of the OR EXCLUSIVE" circuit Cl supplies the modulo sum 2, c,,=a,, U b,,, of the digits a, and b,,. The resulting voltage on terminal 5 representing this sum is applied to input terminal 4 of circuit C2 and, as a control voltage c,,, to terminal 7 of the switch circuit H. At the same time, terminal 6 of circuit C2 supplies the modulo sum 2, S,,=(a,, U b,,) U R,,,, of (a, U b,,) and R,,,, (or R in the first stage). If a,, U b,, is equal to binary l, the corresponding control voltage 4/5 V applied to terminal 7 and hence, to the bases of transistors T1 and T2, is equal to or greater than the selected representative voltages applied to the input terminals 9 and of the IF switch circuit H and hence, to the collector of transistor T1 and the emitter of transistor T2. As a result, transistor T1 is rendered conductive while transistor T2 is blocked, whereby a voltage representing the carry R,,,, is applied to output terminal 8 as representative of the carry R resulting from the addition of a,,, b, and R,,,,.

Similarly, if a,, Ub is binary 0, the zero voltage representative thereof is applied at terminals 5 and 7. Since this voltage is equal to or less than the voltages applied to terminals 9and 10, transistor T1 will be blocked while transistor T2 becomes conductive. A voltage representative of a,, will therefore be applied to output terminal 8 through terminal 10 and transistor T2 as representative of the carry R,,. It will thus be apparent that the carry R,, is obtained simultaneously with the addition of the digits a,,, 12,, and the carry R,,,,, thereby eliminating the carrying propagation time which is inherent in prior-known binary adding devices.

The foregoing operation of the device utilizing circuits C1 and C2 for performing the logical 0R EXCLUSIVE function can be summarized by means of the following table which illustrates the sum 8,, and the carry R,, resulting from the addition of the sum a,,+b,, to a carry R,,,,.

a, 0 1 0 1 0 1 0 1 11,, o o 1 1 0 0 1 l a, u b, o 1 1 0 o 1 1 0 R,,,, o o 0 o 1 1 1 1 s, 0 1 1 o 1 0 0 1 R, o 0 1 o o 1 1 1 In the specific form of the invention shown in FIGS. 2 and 3, the circuits Cl and C2 are identical and each is illustrated as the mirror image of the other. Hence, only circuit C1 will be described in detail. Said circuit comprises a comparator D, of the type disclosed in my US. Pat. No. 3,348,199, a NOT circuit E, and a voltage regenerator or amplifier circuit F,. The comparator circuit D, comprises a transistor T3 having an emitter, a collector and a base, the latter being connected through equal resistances r, and r, to input terminals 1 and 2, respectively. The emitter is connected through a resistance R3 to a bus bar 11 which is in turn connected to ground and hence, to the low-potential terminal of a source of voltage V,,. The collector is connected through a resistance R5 to an output terminal 12 and further through a resistance R7 to the bus bar 14 emanating from the high-potential terminal of the source of voltage V,,. The resistances r, and r are of equal value and small in comparison to, say one-half the size of, resistances R3 and R5 which are in turn of equal value.

The output terminal 12 of comparator D, is connected to the base of a transistor T5 of the PNP-type, the emitter of which is placed under voltage through a lead 15 and resistance R15 connected to bus bar 14. The collector of transistor T5 is connected to bus bar I] through a resistance R9. The latter and transistor T5 form a NOT" circuit E, having an output terminal 16.

The regenerator or amplifier circuit F, comprises an NPN- type transistor T7, the collector of which is connected to bus bar 14 through resistance R13. The emitter is connected to output terminal 5 of circuit C1 and thence, through a resistance R11 to bus bar 11. The base of transistor T7 is connected to output terminal 16 of circuit E,. The emitter of the corresponding transistor T8 is connected to the output terminal 6 of circuit C2, and the input terminals 3 and 4 of said circuit are connected, as in FIG. 1, to input terminal 9 and control terminal 7 of switch circuit H.

In order to simplify the description and facilitate undcrstanding the mode of operation of the circuit C1 in performance of the logical OR EXCLUSIVE function, we may again and by way of example, adopt the voltages 4/5 V,, and OXV, as representative or indicative of the binary numbers 1 and 0, respectively. Bus bars or conductors l5 and 11 are accordingly brought to these voltages, respectively, by suitably selecting resistances R15 and R16 (see FIG. 3) and connecting bar 11 to ground. Similarly, resistance R13 is selected to be equal to one-fourth of resistance R11, and resistances R3, R5 and R7 are made equal to one another.

When one now applies to input terminals 1 and 2 potentials indicative of digits a,, and b,, and having values adopted as representing binary digits 0 and l or I and 0, respectively, i.e., OXV, and 4/5V,,, or 4/5V,, and 0XV,,, the base of transistor T3 will have a potential 2/5V Since the latter exceeds the potential of the emitter, the transistor T3 saturates. The voltage difference between the collector and emitter becomes small, and the combination of resistances R3, R5 and R7 becomes in effect a voltage bridge divider. As a result the potential 2/3 V, at terminal 12 and hence, on the base of transistor T5, will be less than the potential 4/5V of the emitter of said transistor. Accordingly, this transistor assumes a saturated state, thereby raising the potential of terminal 16 and the base of transistor T7 to a positive value. Transistor T7 accordingly becomes saturated, and the potential at output terminal 5 of circuit C1 attains the value 4/5V,, representative of binary digit l according to the adopted convention. Thus, if either one but not both of digits a,, and b,, is binary l, the output signal at terminal 5 of the OR EXCLUSIVE" circuit Cl will be representative of binary 1.

If, on the other hand, the potentials applied to input terminals I and 2 are both null, as when both 11,, and b,, are binary 0, all three transistors T3, T5 and T7 will be blocked. Transistors T3 and T7 will be blocked since the voltages of their bases will be less than the voltages of their respective emitters. Transistor T5 will be blocked by reason of its base voltage being superior to its emitter voltage. In this event the voltage at output terminal 5 will be null and hence, representative of the binary digit 0.

The only remaining possibility is when a, and b, are both binary l and the voltage applied to both terminals I and 2 is 4/5V In this case, transistor T3 becomes saturated, the potential of its base being superior to that of its emitter. However, by reason of the low resistance of the base to emitter junction of the transistor, the circuit D becomes in effect substantially equivalent to the four resistances r,, r 173 R3 and R5, all connected at one extremity to the transistor and being, therefore, in short circuit. As a result the potential of terminal 12 and hence, of the base of transistor T5 will be superior to that of its emitter if the value of the resistances R3 and R5 is sufficiently great in comparison to resistances r and r for ex ample, twice as great. Transistors T5 and T7 will then be blocked, and the potential at terminal 5 remains null and hence, representative of binary O.

Thus, the circuit CI as disclosed in FIG. 2 will supply the binary number 1 whenever one, but only one, of the digits a, and b, is binary I. In all other cases, the circuit supplies binary at output terminal 5. This OR EXCLUSIVE output a, U b,, of circuit C1 is applied, according to the invention, to the input terminal 4 of circuit C2 and also as a control signal to terminal 7 of commutator H. The combined circuits of FIG. 2 will accordingly function in the manner described above for the adding device of FIG. 1, and it will be seen from the foregoing table that for all possible combinations of values for a b, and R when the OR EXCLUSIVE output a, U b, is binary 0, the carryover R, is equal to a, and when the output a, U b is binary I, the carryover R, is equal to R,,,,. Thus, in adding the digits of each rank in two binary numbers the carryover R from the next lower or preceding rank of digits is included in the addition, and the carryover R,, to be added in with the digits of next higher rank is simultaneously obtained.

If one now accepts or adopts as a convention that the binary digits I and 0 are represented by the voltages 0 V,, and 4/5 V,,, respectively, the circuits Cl and C2 will perform the logical COMPARATOR function which is the complement of the OR EXCLUSIVE function described above. This operation is exemplified by the following tables in which a,,, b, and are, respectively, the voltages or corresponding binary digits applied to input terminals 1 and 2 and the voltages or digits which appear on output terminal 5 ofcircuit Cl:

It will be seen from these tables that the voltage at output terminal 5 is equal to 0 V, representing binary 1 according to the adopted convention when 11,, and b,, are equal and that the voltage at output terminal 5 is equal to 4/5 V representing binary 0 when a and b are different or unequal. We may, therefore, writethe equation the sign being used to designate or exclusive complement operation.

Similarly, one obtains on the output terminal 6 of the COMPARATOR" circuit C2 (FIG. 4) the following result:

wherein 6 represents the output voltage on terminal 6 and hence, the binary digit represented by said voltage.

There remains for consideration the operation of the IF switch circuit H in conjunction with circuits Cl and C2 functioning as COMPARATOR circuits. As pointed out above, if the control voltage applied to output terminal 5 and hence, to control terminal 7, is equal to 4/5 V the transistor T1 of the NPN-type is conductive, and the transistor T2 of the PNP type is blocked. Also, if the control voltage on terminals 5, 7 is equal to 0 V,,, the transistor T2 is conductive, and transistor T1 is blocked. Accordingly, the following formulas are applicable to the operation of the IF switch:

In the first-mentioned case, a, and b, are unequal, and R, is transmitted to terminal 8 via transistor T1. In the last-mentioned case, a, and b, are equal, and R, is transmitted via transistor T2. In order that the fictitious carry R, introduced into the first stage on terminal 9 will be binary 0, represented by the voltage 415 V,,, the switch blade 21 of circuit G should contact terminal 23.

The following table illustrates the OR EXCLUSIVE COM- PLEMENT operation of the circuits of FIGS. 2 and 3 under the convention that the binary digit 1 is represented by the voltage OXV and binary digit 0 is represented by the voltage 4/5 V,,, it being understood that the switch blade 21 is in contact with terminal 23 in order that binary 0 will be applied to the first stage on terminal 9:

an 0 1 0 1 0 1 0 l bu"... 0 0 1 1 0 0 1 1 anbn 1 0 0 1 1 0 0 1 R 0 0 0 0 1 1 1 1 Sn 0 1 1 0 1 0 0 1 Rn 0 0 0 1 0 1 1 1 It will be understood that the IF, COMPARATOR" and OR EXCLUSIVE" circuits, the latter being sometimes referred to as a HALF-ADDING" circuit, disclosed herein may have other known COM PARATOR," OR EXCLU- SIVE or HALF-ADDING circuits substituted therefor in the adding devices comprehended by the invention. The IF switch circuit may, if desired, be formed of a known combination of classic NOT, OR" and AND" circuits by means of Boole s algebra on the basis of the following table with the following values in which 9, l0, 7 and 8 symbolize the numbers or voltages applied upon electrodes 9, l0, 7 and 8:

In the modifications of the invention hereinafter described, novel OR EXCLUSIVE or COMPARATOR circuits are employed wherein the input terminals are separated from the output terminals, and novel IF switch circuits are employed wherein the control terminals are separated from the input and output terminals, the output networks of these circuits being controlled by radiations from the input networks thereof. As in the embodiment of FIG. 1, each adder stage of these modified embodiments comprises, as illustrated in FIG. 5, a commutator or IF switch circuit H having two input terminals 31 and 32, an output terminal 33 and a control terminal 34 and two preferably identical OR EXCLUSIVE or COMPARATOR circuits Cl and C2 having input terminals 35, 36 and 37, 38 and output terminals 39 and 40, respectively. Terminals 31, 36 and terminals 34, 38, 39 are connected to each other and terminals 32 and 37 are connected to a conductor 41 which transmits the signal representative of the carry R,,,, from outlet terminal 33 of a preceding stage or R,, from a circuit G. As will be more fully described below, the switch H (FIG. 5) is capable of selectively connecting its output terminal 33 to one of the input terminals 31 or 32 if one applies on control terminal 34 a voltage representative of binary digit 1 and of connecting terminal 33 to the other of said input terminals if a voltage representing binary is applied to its control terminal 34. Accordingly, this switch is properly designated a logical IF switch.

The novel OR EXCLUSIVE" or COMPARATOR circuit C1 of FIG. is illustrated separately in FIG. 6 as being connected across the terminals 43, 44 of a source 42 of voltage V,, by means of bus bars 45 and 46, the latter of which may be grounded. Between the bars 45 and 46 there are arranged in series one photoelectric resistor 47 and an impedance 50. One of the extremities of the latter is connected to the bar 46, and the other extremity is connected to the output terminal 39. The input terminals and 36 of this circuit are connected to a gaseous discharge lamp 5]. An impedance 52 is preferably inserted in input line 35, and a second impedance 53 is preferably connected across lamp 51. Photoelectric resistor 47 and lamp 51 are enclosed in an opaque housing 54, whereby the lamp constitutes the only light source capable of illuminating the resistor.

The photoelectric resistor 47 may be, by way of example, a commercially available resistor, the value of which may vary between 50 kilohms and 200 megohms, depending upon whether the same is or is not illuminated. Lamp 51 may, by way of example, be a commercially available unpolarized Neon discharge lamp having a striking voltage of one one-hundredth of a volt and a consumption of one-fourth to l milliampere in direct current or alternating current of a frequency of l megacycle per second. When a resistor and lamp of this type are employed, the value of the voltage V,, of source 42 may be of the order of 200 volts, and the values of impedances 50, 52, and 53 may respectively be 1 megohm, 200,000 ohms and l megohm. The impedance 53 acts to prevent the uncontrolled lighting of lamp 5] under the possible effect of a photoelectric resistor (not shown) similar to resistor 47 and series connected with terminal 35 or 36.

If voltages V max and V min having a difference greater than the striking voltage of lamp 51 are applied to terminals 35 and 36 (FIGS. 5 and 6) the lamp 51 will illuminate resistor 47, and the value of the latter will accordingly drop from 200 megohms to 50 kilohms. Resistor 47 is thus rendered conductive, and the voltage on output terminal 39 becomes equal to V,,. If, however, the voltages applied to terminals 35 and 36 have a difference less than the striking voltage of lamp 51, such as when either V max or V min is applied to both terminals, the lamp remains dark, the value of resistance 47 remains at 200 megohms and the voltage applied to terminal 39 remains at substantially 0, the same as bus bar 46.

This operation of the circuit of FIG. 6 and hence, of circuit C1 of FIG. 5, is summarized in the following table (A) which I illustrates the resultant voltage on terminal 39 for the various combinations of signal voltages applied to terminals 35 and 36:

In view of the fact that input network 35-36-51-52-53 and the output network 3947-50 are completely electrically independent of each other, one can represent the binary digits 1 and 0 (or the corresponding symbols and on the input network by means of signal voltages V max or V min applied to terminals 35 and 36. On the output network, the binary digits 1 and 0 may be represented either by signal voltages V, and 0 or 0 and V,, applied to terminal 39. The following tables (B) and (C) which illustrate the respective binary values of voltages applied to terminals 35, 36, and 39 are then equivalent to table (A). Table (B) illustrates that the circuit of FIG. 6 performs the logical COMPARATOR function on the basis of the convention that the binary digits 0 and l are respectively represented by V max and V min and by voltages V and 0. Table (C) illustrates that said circuit performs the logical OR EXCLUSIVE? or HALF-ADDING function when one adopts the convention that binary digits 1 and 0 are respectively represented by input voltages V max and V min and by output voltages V,, and 0:

I o o o I 0 o o I as so 39 o o o o I I 1 o The novel switch circuit H of FIG. 5 is specifically illustrated in FIG. 7 as comprising electrically independent input and output networks. The input network comprises the source 42 of voltage V and bus bars 45 and 46 which may be the same as in FIG. 6. Two gaseous discharge lamps 55 and 56 are connected between control terminal 34 and the bus bars 45 and 46, respectively. lmpedances 57 and 58 are preferably connected in series with lamps 55 and 56, respectively, and impedances 59 and 60 are connected in parallel with said lamps. The output network comprises two input terminals 31 and 32, an output terminal 33 and two photoelectric resistors 61 and 62 connected between terminals 31, 33 and32, 33,

respectively. Resistors 61 and 62 are disposed for illumination by lamps 55 and 56 in opaque housings 63 and 64, respectively. When this switch circuit is used in combination with two circuits according to FIG. 6 in the adding device stage of FIG. 5, the lamps 55, 56 and photoelectric resistors 61, 62 may be similar to lamp 51 and resistor 47, respectively. lmpedances 57 and 58 may have a value of 200,000 ohms and impedances 59 and 60 may have a value of 1 megohm.

If one applies to control terminal 34 a voltage equal to V,,, lamp 56 will be energized to illuminate resistor 62, while lamp 55 remains dark. The value of resistor 62 accordingly drops to 50 kilohms, while the value of resistor 61 remains at 200 megohms. As a result the voltage applied to output terminal 33 becomes substantially equal to that applied to terminal 32.

If, on the other hand, one applies voltage on control terminal 34, the lamp 55 will be energized to illuminate resistor 61 while lamp 56 remains dark. The value of resistor 61 will accordingly drop to 50 kilohms, and the voltage applied to terminal 33 will become substantially equal to that applied to terminal 31. It will thus be seen that output terminal 33 is connected to input terminal 31, if the voltage on control terminal 34 is 0 and to input 32 if the voltage on control terminal 34 is equal to V,,. Accordingly, the switch circuit illustrated in FIG. 7 may be properly designated as a logical IF circuit.

By adopting the convention to represent binary digits 0 and l by voltages V,, and 0 applied to control terminal 34 and by means of different signal voltages V max and V min applied to terminals 31 and 32 and hence, alternatively to output terminal 33 it becomes possible to draw up the following tables (D) and (E) wherein respective binary vaLues of the voltages applied to terminals 31, 32, 34, and 33 are compiled, table (D) being based on the convention that V, represents binary l and table (E) being based upon the convention that V,, represents binary O:

0 0 O O 0 l 0 0 l 0 0 l l I O I 0 0 l 0 0 l l I l 0 l 0 0 O l 0 0 l l 0 l 0 l l l I l l 0 0 0 0 0 l O I l 0 0 0 l 1 0 Considering now the binary adder stage of FIG. which is made up of a switch circuit H as shown in FIG. 7 and two circuits as shown in FIG. 6, it will be noted that the housings 54, 63, and 64, as well as the impedances 52, 53, 57, 58, 59, and 60, have been deleted in the interest of clarity and in circuit C2, which may be identical with circuit C1, the radiation transmitter or lamp is designated 51a, the photoelectric resistnr is desionated 47a. and the impedance is designated 50a.

'COMPLEMENT output an By adopting the convention that the voltages 0 and V, represent binary digits 1 and 0, respectively, it will now be shown that the circuit of FIG. 5 is, like the circuit of FIG. 2, capable of performing the addition of two digits a, and 12,, of equal rank n in two binary numbers A and B and a carry R resulting from the addition of two digits a and 12,, of next lower rank and an applicable carry. Thus, when the digits a,,-, b,, and R, are applied in the form of representative signal voltages on the terminals 35 and 36 and conductor 41 and hence, on terminals 32 and 37, the resulting voltage on terminal 39 and hence, on terminals 34 and 38, will be equal, in accordance with tables (A) and (B), to OR EXCLUSIVE voltage applied to output terminal 40 of circuit C2 will represent the OR EXCLUSIVE COMPLEMENT If an and b are unequal, then m,@ b,l equals binary 0 .and the voltage applied to output terminal 39 and hence, 20

to control terminal 34 becomes equal to V1, in accordance with the adopted convention. The output terminal 33 will then, as explained above, become connected through resistor 62 to terminal 32. Accordingly, the voltage applied to terminal 33 will correspond to the voltage re resenting R,, (or R If, however, a and b,I are equal, 011 b" will equal binary 1, represented by zero voltage on terminals39 and 34. With zero voltage applied to terminal 34, lamp 55 is energized and resistor 61 is illuminated and rendered more 1 0 1 0 1 0 1 0 1 I 0 0 1 1 0 0 1 1 O 0 1 0 0 0 1 I 1 1 1 I 0 1 0 O 1 0 O 1 0 1 1 1 It will be seen from table (F) that for all combinations of the digits a,,, b, and R S. is equal to the modulo sum 2 of said digits and that R, is equal to the carry resulting from the addition of said digits. It will be seen, also, that in accordance with the operation of the circuit of FIG. 5, as described above, R, s uare, whenever a,. b,l is binary 0 represenied by a voltage V, on control terminal 34, and that R, equals an whenever a,.b,l is binary 1 represented by zero voltage on .control terminal 34.

By adopting the convention complementary to that employed in the compilation of table (F); that is, by representing the binary digits land 0 by voltages V, and 0, respectively, the OR EXCLUSIVE mode of operation of the adder stage of FIG. 5 can be demonstrated by the compilation in table (G) below, the values being inferred from the complementary table (F) by changing binary 1 to 0 and vice versa:

It will be seen that in this table S, and R, remain equal respectively to the modulo sum 2 of various selected combinations of the digits a,,, b,, and R, and to the carry resulting 5 from the addition of said digits. On the third line a, U b, in-

b,,. Similarly, the resultant dicates the OR EXCLUSIVE output of the logical operation achieved by circuit C1. Thus, the tables (F) and (G) are identical with the foregoing corresponding tables which symbolize the OR EXCLUSIVE COMPLEMENT and OR EX- CLUSIVE operations of the adder stage circuit of FIGS. 1 and 2.

Asis true with the circuit of FIG. 2, one may in the utilization of FIG. 6 adopt voltages having the values and V,, or V,, and 0 to represent the binary digits 1 and 0, respectively. In either case the carry R, is achieved and introduced into the cells of the adding device in the form of a signal voltage, as distinguished from the state of a switch, with the advantageous result that carry propagation time is eliminated. Additionally, the systems of FIGS. 2 and 5 do not use the complements of any digits, and hence eliminate the necessity for a substantial number of conductors and other components required in prior-known binary adders. A further advantage resides in the fact that the signal voltages V max and V min and V,, and 0 representing the binary digits may vary between wide limits, the differences V max-V min and V,,O having simply to remain in excess of the striking voltage of the discharge lamps.

It is a requirement that lamps 51 and 51a (FIGS. 5 and 6) be unpolarized in order that the same may be energized irrespective of the direction of the passage of current between terminals 35,36 and 37,38. However, since current always passes through radiation-responsive elements 47 and 47a in the same direction, it is possible to replace the photoelectric resistors by photodiodes, light-controlled solid thyratrons or phototransistors.

Thus, the modified comparator circuit illustrated in FIG. 8 is identical with FIG. 6 except that the radiation or lightresponsive element 47 is constituted by a phototransistor having a base 65, an emitter 65a and a collector 65b. In this embodiment a l2-volt source 42 is adequate and preferable, and the value of resistor 50 may be of the order of kilohms.

If the lamp 51 is switched off, the base 65 of the phototransistor is in darkness, and the current passing the collector 65b and the emitter 65a has a low value. The intensity of this current greatly increases if the lamp 51 illuminates the base 65 of the transistor. As a result, two voltages are applied to terminal 39 having sufficiently different values to represent the binary digits l and 0 in accordance with the convention heretofore specified. The operation of the circuit of FIG. 8 corresponds therefore to the table (B) and the table (C) referred to above and may be substituted for the comparable circuits in the adding device of FIG. 5.

As illustrated in FIGS. 9 and 10', each of the unpolarized light-emitting elements 51, Slain circuits C1, C2 of FIGS. 5 and 8 may be replaced by two polarized light emitters, such as by two' gallium arsenide laser diodes 66 reversely connected in parallel (FIG. 9) or by a single such diode 66 in combination with a full-wave rectifier (FIG. 10). In the form illustrated the rectifier is of the bridge type comprising four diodes 67 connected in a well-known manner between input terminals 35, 36 with diode 66 connected across output terminals 68 and 69. In FIG. 9 either diode 66 may illuminate the same lightresponsive element 47 which may be of any suitable type, such as the phototransistor shown.

In the circuit of FIG. 10, which may be substituted for the circuits C1, C2 of FIG. 5, the light-responsive or radiationreceiving element 47 is illustrated in the form of a photoelectric diode. This diode is connected to output terminal 39 by suitable amplifier means 71 which may comprise a transistor 82 having its base and emitter junction connected across the diode by means of leads 39a and 46. The emitter-collector junction of the transistor is connected across bus bars 45, 46, preferably through a load 83, and the output terminal 39 is connected to the collector.

Inasmuch as the radiation-emitting elements 55, 56 of the input network of the switch circuit H of FIGS. 5 and 7 may be polarized other suitable emitters may be used in place of the Neon lamps mentioned above. For example, laser diodes may be substituted as illustrated in FIG. 11 and zener diodes 70,

70' may be provided to guard against undesired or improper lighting of the laser diodes. Similarly, the radiation responsive elements 61, 62 of switch H may also be in the form of photoelectric transistors as shown in FIG. 11, said transistors being rendered conductive when the bases 72 and 73 thereof are illuminated by their respective laser diodes or other suitable light emitters.

The invention also contemplates novel logical circuits which employ other types of radiation emitting and responsive devices and which are adapted for use as components in electronic binary adders of the types described above. For example, the novel comparator circuit disclosed in. FIG. 12 employs electromagnetic radiations for effectively coupling the input network to the output network thereof. The input network comprises a full-wave rectifier consisting of four diodes 67 arranged in a known manner and connected to input terminals 35, 36. A negative resistor or Esaki diode 74 is connected across the output terminals 68, 69 of the rectifier and in parallel with a main capacitor 75 and with the series-connected coil 76 and auxiliary capacitor 77, the latter serving to prevent the passage of direct current to the coil. The parallel-connected elements 74-77 constitute a generator and emitter of electromagnetic waves upon application of unequal voltages to terminals 35 and 36. The negative resistance of the Esaki diode serves to suppress the damping of the oscillating circuit constituted by coil 76 and capacitors 75, 77.

The output network of the circuit of FIG. 12, which may be used for circuits C1 and C2 of FIG. 5, comprises a coil 78 inductively coupled to the coil 76 and a capacitor 79 connected in parallel therewith between a conductor 39a and bus bar 46. This unit 78, 79 constitutes a receiving oscillating circuit matched to the emitter described above. The connection between conductor 39a and output electrode 39 is achieved by means of a rectifier 80, for instance a diode, and a suitable amplifier 71 which may be constructed as heretofore described.

In the modification of FIG. 13 the radiation emitter 51 is constituted by a Gunn diode 74 connected across the terminals 68, 69 of a full-wave rectifier 6767 supplied by input terminals 35, 36. Diode 74 supplies electromagnetic oscillations of a frequency on the order of 10,000 to 20,000 megacycles per second which are received by a diode 80 housed therewith in a suitable cavity resonator 84. Diode 80 is connected to output terminal 39 through an amplifier 71 connected across bus bars 45, 46.

In a further modification (FIG. 14) the terminals 35, 36 and conductors 39a, 46 are connected, respectively, to an emitter antenna and to a receiver antenna 86. The unit, constituting the comparator circuit, or at least the rectifier bridge, the Gunn diode 74 and the two antennas, may be mounted on a plate 87 made up, for instance, of dielectric glass. The length L of these antennas is equal to the half-wavelength of the electromagnetic oscillations generated by means of the diode 74.

As illustrated in the drawing the input network preferably comprises a resistor or shock impedance 88 inserted between one of the electrodes 35 or 36 and an input terminal of a bridge rectifier 6767, a Gunn diode 74 connected across terminals 68, 69 of the bridge and the emitter antenna 85 connected at points 90, 91 to tern 1inals 69, 68. The diode 80 of the output network is connected to the receiver antenna 86 at a point 93 and to output terminal 39 by means of a resistor 94 and an amplifier 71 constructed as already described. Another point 92 on antenna 86 is connected to the emitter of transistor 82 of the amplifier. The maximum and minimum signal voltages to be applied to the input electrodes 35, 36 should likewise be 12 volts and 0 volts. If the frequency of the electromagnetic oscillations generated by diode 74 is assumed, by way of example, to be 21,000 megacycles per second, the length L of the antennas 85, 86 should be equal to 7 millimeters. It will be seen that the coupling between the diode 74 and antenna 85 and between the transistor 82 and the antenna 86 is accomplished by means of the antenna lengths between the points 90, 91 and the points 92, 93, respectively. FIG. 15 shows a circuit very similar to FIG. 14

and, by way of example, the values that may be adopted for the resistors 83, 88, 94 and for the voltages of the bars 45, 46 in the circuit of FIG. 14.

In another modification (FIG. 16) the radiation emitter 51 and the radiation receiver 47 are made up of barium titanate plates metallized along their faces 95, 95a and 96, 96a and a glass plate 84 inserted therebetween. The terminals 35, 36 constitute the output terminals of two multiplier or modulator blocks 97, 98, for instance of the ring or phase modulation type, provided with input terminals 35a, 36a and supply terminals 99, 100 connected to a high-frequency current source 101, said frequency being, forexarnple, of the order of 3 megacycles per second.

Upon sending direct current signals 102, 103 to terminals 35a, 36a the output signals 102a and 103a modulated in the blocks 97, 98 cause a vibration of the glass plate 84. The voltages 104 picked up on the output electrode 39 are then rectified to signal 104a by means of the diode 80.

However, if the signals 102 and 103 applied to electrodes 35 and 36 are voltage pulses (FIG. 17) a voltage pulse 104 is applied to the output terminal 39 and is rectified by the diode 80 to signal 104a. The current source 101 and the modulator blocks 97, 98 may then be eliminated.

The embodiment of FIG. 18 is the same as that of FIG. 16, except that it provides a radiation emitter-receiver unit 51-84-47 which resorts to the propagation of mechanical agitations in a solid or liquid medium, such as a bar 84 made of nickel, quartz, mercury or the like. In such an OR EXCLU- SIVE" circuit comprising, for example, a mercury column 84, a piezoelectric emitter crystal 51 and a piezoelectric receiver crystal 47, the signals 102, 103 to be transmitted are first modulated in the blocks 97, 98 to a frequency of some 10 megacycles per second before being applied to the crystal 51 so as to cause it to vibrate. This crystal creates ultrasonic trains in mercury column 84 causing the vibration of receiver crystal 47. The resulting signal 104 applied to terminal 39 is amplified in a block 105 and then demodulated in a block 80 prior to its regeneration in a block 106.

In FIGS. 19, 20, 21, 22 and 23 there are illustrated logical IF switch circuits which may replace those heretofore described in an adding device and which make use of emitter and receiver networks similar to those embodied in the circuits of FIGS. 12, 13, 14, 15 and 17, respectively,.

The IF switch of FIG. 19 comprises, for example, an

emitter constituted by a negative resistor or by an Esaki diode 107, a main capacitor 110 and a coil 111 series arranged with an auxiliary capacitor 112 that prevents the passing of a direct current into the coil. The unit comprising elements 107, 110, 111 and 112 constitutes an emitter 55 of electromagnetic waves upon application of a voltage equal to volt to control terminal 34, the negative resistance of the Esaki diode being operable to suppress the damping of the oscillating circuit constituted by the coil 111 and the capacitors 110, 112. The shock impedances 113, 114 are preferably inserted between emitters 55, 56 and control terminal 34 of the switch.

, The receiver cooperating with emitter 55 comprises a coil 115 inductively coupled to the coil 111 and a capacitor 116 connected in parallel with coil 115, the unit 115, 116 constituting a receiver circuit matched to the emitter 55. This receiver circuit is connected to the emitter of a transistor 118 and, by means of a diode 117, to the base of said transistor, for instance of the NPN-type, the emitter and collector of which are respectively connected to the output terminal 33 and input terminal 31 of the switch circuit.

The emitter 56 and the receiver 62 are identical with emitter 55 and receiver 61, respectively, the corresponding parts thereof being identified by the same numerals with an added a. The emitter and collector of transistor 118a are, however, connected to input terminal 32 and output terminal 33, respectively. The moment emitter 55 (FIG. 19) sends electromagnetic waves onto receiver 61 there is generated in this receiver a pilot current going from the base of the transistor toward its emitter or towards its collector. This current starts the passage of a voltage signal between the electrodes 31 and 33. The functioning of the emitter 56 occurs when a voltage V,, is applied to terminal 34 and results in the passage of a voltage signal between the terminals 32 and 33 via the emitter-collector junction of transistor 118a.

In the embodiment illustrated in FIG. 20, the radiation emitters 55, 56 are constituted by identical Gunn diodes adapted to generate electromagnetic oscillations of the order of 10,000 to 20,000 megacycles per second and disposed at one extremity of cavity resonators 119, 119a. These oscillations are received by means of the diodes 117, 117a disposed at the other extremities of said cavity resonators and connected across the base-to-emitter junctions of the transistors 118, 118a. The emitter terminals of said transistors are also connected to the output electrode 33, and the collector terminals thereof are connected to input terminals 31 and 32, respectively.

In the modification of FIG. 21 Gunn diodes 107, 107a are connected by means of conductor wires 120, 121 and 120a,

121a to emitter antennas 122, 122a at points 123, 124 and 123a and 124a. The rectifier diodes 117, 117a are connected to the receiver antennas 125, 125a at points 127 and 127a and to the bases of transistors 118, 118a, for instance by means of resistors 130, 13011, the collector terminals of the transistors being connected to the output terminal 33 of the IF switch. The emitter terminals of said transistors are connected to points 126, 126a on the antennas 125, 125a and to input terminals 31 and 32. The length L of the antennas 122, 122a, 125 and 125a is equal to the half-wavelength of the electromagnetic oscillations generated by means of the Gunn diodes 107, 107a, the connection of the antennas with the diodes 107, 107a and transistors 118, 118a being carried out as a result of the lengths situated between the points 126, 127 and 126a, 127a. Glass or other dielectric plates 131, 131a carry at least the Gunn diodes and the four antennas.

The embodiment of FIG. 22 is very similar to FIG. 21, the only difference being that the diodes 117, 117a are connected between the antennas 125, 125a and the emitter terminals of transistors 118, 118a.

FIG. 22 also illustrates the values which may be adopted for the impedances 113, 114, 130 and 130a and for the voltages of the bars 45, 46 in FIG. 21. The maximum and minimum voltages of the signals applied to electrodes 31, 32, 34 should likewise be 10 volts and 0 volt. The operation of the switch circuit of FIGS. 20 to 22 is identical with or very similar to that of the switch of FIG. 19.

In the IFf switch of FIG. 23 the emitters 55, 56 and the corresponding receivers 61, 62 are constituted by barium titanate plates metallized along their faces 132, 132a, 133, 133a, 134, 134a, 135, 135a, and glass plates 119 and 1190 are sandwiched therebetween. The metallized surfaces of the receivers 61, 62 are connected across loads, for instance resistors 138, 138a, and across the base-to-emitter junctions of transistors 118, 118a, the connection between the receivers and the transistor bases being also in this case provided by means of rectifier diodes 1 17, 117a.

If a O-voltage impulse is applied to the terminal 34 (FIG. 23) emitter 55 causes the glass plate 119 and the receiver 61 to start vibrating, thereby creating a current impulsein the load 138. This impulse rectified by means of the diode 117 travels from the base of the transistor 118 towards its emitter, thereby permitting the passage of a voltage impulse between the electrodes 31 and 33. The application of an impulse voltage V on the electrode 34 causes, on the contrary, the passage of a voltage signal between the electrodes 32 and 33.

In order to form according to FIG. 5 an adding stage having the OR EXCLUSIVE circuits and the IF" switch circuits referred to above, it will, as a rule, be of interest, but not necessary, to combine the modifications which comprise similar elements, such as those in FIGS. 6 and 7 or 9, 10 and 11 or 12 and 19 or 13 and 20 or 14 and 21 or 17 and 23. However, circumstances well known to a person skilled in the art of logical circuits may give rise to the desirability of a different 

1. The method of electronically adding digits of equal rank in two binary numbers and a carry represented by selected electrical voltages indicative of binary 1 and 0, which comprises applying the voltage representing the digit an of rank n in one of said numbers to one input terminal of a first logical comparator circuit and to one input terminal of a logical ''''IF'''' switch circuit and applying the voltage representing the digit bn of rank n in the other of said numbers to the other input terminal of said first comparator circuit, thereby producing a resultant voltage representative of binary 1 or 0 on the output terminal of said first comparator circuit depending upon the equality or inequality of said digits, applying the voltage representing the binary carry required to be added to the sum of said digits to the other input terminal of said ''''IF'''' switch circuit and to one input terminal of a second comparator circuit, and applying said resultant voltage to the other input terminal of said second comparator circuit and to the control terminal of said ''''IF'''' switch circuit and thereby energize the switch circuit to connect its output terminal to one or the other of its said input terminals depending upon the value of said resultant voltage applied to said control terminal.
 2. A method as defined in claim 1 wherein the binary digit 1 is represented by the larger of said selected voltages and the binary digit 0 is represented by the smaller of said selected voltages, whereby the comparator circuits perform the logical ''''OR EXCLUSIVE'''' function.
 3. A method as defined in claim 1 wherein the binary diGit 1 is represented by the smaller of said selected voltages and the binary digit 0 is represented by the larger of said selected voltages, whereby the comparator circuits perform the logical ''''OR EXCLUSIVE'''' complement function.
 4. A method as defined in claim 1 wherein the equality or inequality of the input voltages applied to the input terminals of each of said comparator circuits is determinative of the resultant voltage on the output terminal thereof and wherein the latter voltage is representative of the sum of the binary digits represented by the input voltages.
 5. A method as defined in claim 1 wherein the magnitude of the difference between voltages applied to the input terminals of each of said comparator circuits is determinative of the resultant voltage on the output terminal thereof and wherein the latter voltage is representative of the sum of the digits represented by input voltages.
 6. A method as defined in claim 1 wherein the voltage applied to the output terminal of said switch circuit is representative of the carry resulting from the addition of said digits and said first-named carry.
 7. A method as defined in claim 1 which further comprises applying the voltage representing the digit an 1 of next higher rank in said one number to one input terminal of a third logical comparator circuit and to one input terminal of a second logical ''''IF'''' switch circuit and applying the voltage representing the digit bn 1 of next higher rank in said other number to the other input terminal of said third comparator circuit, thereby producing on the output terminal of said third comparator circuit a resulting voltage representative of binary 1 or 0 depending upon the equality or inequality of the digits an 1 and bn 1, applying said resulting voltage to an input terminal of a fourth logical comparator circuit, and applying the voltage on the output terminal of said first-named ''''IF'''' switch circuit to the other input terminals of said second ''''IF'''' switch circuit and said fourth comparator circuit.
 8. A method as defined in claim 1 which further comprises creating radiated energy in response to the voltages applied to the input terminals of at least one of said comparator circuits, and utilizing said radiated energy to control the resultant voltage on the output terminal of said one comparator circuit.
 9. A method as defined in claim 8 wherein the radiated energy consists of light rays.
 10. A method as defined in claim 8 wherein the radiated energy consists of electromagnetic waves.
 11. A method as defined in claim 8 wherein the radiated energy consists of ultrasonic waves.
 12. A method as defined in claim 8 wherein the radiated energy consists of vibration generated waves.
 13. A method as defined in claim 1 which comprises generating radiated energy in response to voltages applied to the control terminal of said ''''IF'''' switch circuit, and utilizing said radiated energy to control the selective electrical connection of the output terminal of said ''''IF'''' switch circuit to one or the other of said input terminals of said ''''IF'''' switch circuit.
 14. In apparatus adapted for electronically adding corresponding digits of two binary numbers and a carry, said digits and carry being represented by electrical voltages indicating binary 1 and 0, a first logical comparator circuit, a second logical comparator circuit, a logical ''''IF'''' switch circuit, means for introducing the voltage representing one of said digits into the first comparator circuit, means for introducing the voltage representing the other of said digits into the first comparator circuit, means including a first input terminal for introducing the voltage representing said one digit into said switch circuit, means including a second input terminal for introducing the voltage representing said carry into said switch circuit and into said second comparator circuit, and means for introducing the output voltage of said first comparator circuit into said second comparator circuit and into said switch circuit, the latter comprising means responsive to said output voltage for generating radiated energy and means responsive to said radiated energy for alternatively effectively connecting the output terminal of said switch circuit to one or the other of said input terminals.
 15. Apparatus as defined in claim 14 wherein at least one of said comparator circuits comprises means responsive to said voltages introduced therein for generating radiated energy and means responsive to said radiated energy for controlling the output voltage of said one comparator circuit.
 16. Apparatus as defined in claim 14 wherein said means responsive to said output voltage of the first comparator circuit for generating radiated energy comprises first and second radiant energy emitters, said emitters being connected in series across a source of electrical energy and having a common input control terminal for said introduction of the output voltage of said first comparator circuit, and wherein said means responsive to said radiated energy comprises first and second radiant-energy-controlled devices connected respectively to said first and second input terminals and being responsive respectively to radiant energy from said first and second emitter, the output terminal of said switch circuit being common to said devices.
 17. Apparatus as defined in claim 14 wherein the radiated energy is light rays.
 18. Apparatus as defined in claim 14 wherein the radiated energy is electromagnetic waves.
 19. Apparatus as defined in claim 14 wherein the radiated energy is ultrasonic waves.
 20. Apparatus as defined in claim 14 wherein the radiated energy is vibratory waves.
 21. In electrical apparatus comprising a parallel binary adding stage for adding two digits of equal rank in two numbers and one carry, said digits and carry being represented by means of voltages indicating binary 1 and 0, said stage comprising first and second logical comparator circuits, each having two input electrodes and one output electrode and adapted to perform logical ''''OR EXCLUSIVE'''' or ''''OR EXCLUSIVE COMPLEMENT'''' functions, a commutator switch circuit comprising first and second normally nonconductive radiant energy responsive means connected respectively to an input electrode of said first comparator circuit and to an input electrode of said second comparator circuit and having a common output electrode and first and second radiant energy emitters associated respectively with said first and second radiant energy responsive means for rendering the latter electrically conductive, said emitters being connected in series across a source of electrical energy and having a common input control electrode connected therebetween and to the output electrode of said first comparator circuit and to the other input electrode of said second comparator circuit, said common output electrodes being normally effectively electrically disconnected from said first-named input electrodes of said first and second comparator circuits, and said switch circuit being operable to connect said common output electrode to one of said first-named input electrodes if the voltage representing binary 1 is applied to said input control electrode and to connect said common output electrode to the other of said first-named input electrodes if the voltage representing binary 0 is applied to said input control electrode.
 22. Apparatus as defined in claim 21 wherein at least one of said comparator circuits comprises radiant energy emitter means connected to the input electrodes thereof and responsive to voltages applied to the latter, and radiant energy receiver means responsive to energy emitted by said emitter means for impressing a voltage upon the output electrode of said one comparator circuit.
 23. Apparatus as defined in claim 22 wherein said emitTer means comprises a vibration emitter.
 24. Apparatus as defined in claim 22 wherein said emitter means comprises means for radiating light rays.
 25. Apparatus as defined in claim 22 wherein said emitter means comprises means for radiating electromagnetic waves.
 26. Apparatus as defined in claim 22 wherein said emitter means comprises means for radiating ultrasonic waves.
 27. Apparatus as defined in claim 22 wherein said receiver means comprises light-responsive means.
 28. Apparatus as defined in claim 22 wherein said receiver means comprises a photoelectric resistor.
 29. Apparatus as defined in claim 22 wherein said receiver means comprises a photoelectric transistor.
 30. Apparatus as defined in claim 22 wherein said receiver means comprises a photoelectric diode.
 31. A binary adder for two numbers and a carryover represented by means of electrical voltages indicating binary numbers 0 and 1 comprising two logical ''''OR EXCLUSIVE'''' circuits each having two input terminals and a single output terminal, and a commutator circuit comprising two normally nonconductive solid-state switches with the control electrodes thereof connected in parallel to an input control terminal and having a first input terminal, a second input terminal connected to one of the input terminals of one of the ''''OR EXCLUSIVE'''' circuits, the input control terminal being connected to the output terminal of said one ''''OR EXCLUSIVE'''' circuit and to one of the input terminals of the other ''''OR EXCLUSIVE'''' circuit, and an output terminal, said commutator circuit being capable of connecting its output terminal to one of its said input terminals when a voltage indicating the binary number 1 is applied to said input control terminal and of connecting its output terminal to its other input terminal when a voltage indicating the binary number 0 is applied to said input control terminal.
 32. A binary adder as defined in claim 31 wherein one of the ''''OR EXCLUSIVE'''' circuits comprises a comparator, a ''''NO'''' circuit connected to the output of said comparator and a voltage regenerator circuit connected between said ''''NO'''' circuit and the output terminal of the respective ''''OR EXCLUSIVE'''' circuit.
 33. A binary adder as defined in claim 31 wherein said first input terminal of the commutator circuit is connected to the other input terminal of said other ''''OR EXCLUSIVE'''' circuit.
 34. An electronic parallel binary adding device comprising a plurality of stages, each including first and second voltage comparator circuits and a commutator circuit, each of said circuits having two input terminals and an output terminal and said commutator circuit having a control voltage terminal, means for applying to the respective input terminals of the first comparator circuit voltages which are representative of two digits of corresponding rank in two binary numbers and for applying one of said voltages to one input terminal of said commutator circuit, means connecting the output terminal of said first comparator circuit to said control voltage terminal and to one input terminal of the second comparator circuit, means for connecting the output terminal of the commutator circuit of a preceding stage to the other input terminals of said first-named commutator circuit and of said second comparator circuit, whereby the voltage appearing at the output terminal of the second comparator circuit is symbolically representative of a binary digit resulting from the addition of said two digits of corresponding rank and the carryover binary digit represented by the voltage appearing on said commutator output terminal of said preceding stage.
 35. An electronic parallel binary adding device as defined in claim 34, wherein each comparator circuit comprises a transistor having a collector, an emitter, and a base, means including a resistor connecting said collector to one terminal of the source of electrical energy, means iNcluding a resistor connecting said emitter to the other terminal of said source, said resistor being of substantially equal resistance value, means connecting the output terminal of a said comparator circuit to said collector, and a pair of resistors connected in parallel to said base and each to a separate input terminal of the comparator circuit, the resistors of said pair having substantially equal resistance values, said values being low in comparison to the resistance value of said first-named resistor.
 36. A binary adding device as defined in claim 35, wherein said means connecting the output terminal to said collector comprises a logical ''''NO'''' circuit.
 37. A binary adding device as defined in claim 36 wherein said means connecting the output terminal to said collector comprises amplifier means.
 38. An electronic parallel binary adding device as defined in claim 34 wherein said commutator circuit comprises two transistors, one of said transistors being of the PNP-type and the other being of the NPN-type, the collector of one transistor being connected to the emitter of the other transistor and the bases of said transistors being connected each through a resistor to said control voltage terminal, said last-named resistors being of substantially equal value.
 39. Electrical apparatus comprising an electrical comparator having two input terminals and an output terminal, means for applying either of two unequal electrical signals to each of said input terminals, said comparator comprising normally nonconductive electrical switching means adapted to be rendered conductive in response to said input signals when the signals applied to said input terminals are unequal, means for applying an electrical signal to said output terminal when said switching means is rendered conductive, an electrical commutator operatively connected to said comparator output terminal and comprising two normally nonconductive switching devices of inverse types having a common output connection and each having an input connection, the control terminals of said switching devices being connected in parallel to the output terminal of said comparator, and means for applying either of two unequal electrical signals to each of said input connections, only one of said switching devices being adapted to be rendered conductive when a signal is applied to said comparator output terminal and only the other of said switching devices being adapted to be rendered conductive when no signal is applied to said comparator output terminal.
 40. Electrical apparatus as defined in claim 39 wherein said electrical signals are signal voltages.
 41. Electrical apparatus as defined in claim 39 comprising a second electrical comparator having a first input terminal connected to said comparator output terminal.
 42. Electrical apparatus as defined in claim 41 wherein said second comparator comprises a second input terminal connected to the input connection to one of said switching devices.
 43. Electrical apparatus as defined in claim 42 wherein the input connection of the other of said switching devices is connected to one of the input terminals of said first-named comparator.
 44. Electrical apparatus as defined in claim 39 wherein said switching means comprises a single solid-state switching device.
 45. Electrical apparatus as defined in claim 39 wherein said switching devices are solid-state devices.
 46. A binary adder having a plurality of stages wherein each stage includes first and second comparator circuits and a commutator circuit, each said comparator circuit comprising a transistor having a base, an emitter and a collector, a first input terminal connected to said base through a first resistor, a second input terminal connected to said base through a second resistor in parallel with said first resistor, and an output terminal, the output terminal of the first comparator circuit being connected to one of the input terminals of the second comparator circuit, and said commutator circuIt comprising two transistors of inverse types, each having a base, an emitter and a collector, a control terminal connected to the output terminal of the first comparator circuit and to the bases of said two transistors, a resistance connected between said control terminal and each of said last-named bases, a commutator input terminal connected to the collector of one of said two transistors, a commutator input terminal connected to the emitter of the other of said two transistors, and an output terminal connected to the remaining emitter and collector of said two transistors, one said commutator input terminal being connected to one of the input terminals of said first comparator circuit, and the other of said commutator input terminals and the other input terminal of the second comparator circuit being connected to the output terminal of the commutator circuit of a preceding stage.
 47. A binary adder for two numbers and a carryover represented by means of electrical voltages indicating binary numbers 0 and 1 comprising two logical ''''OR EXCLUSIVE'''' circuits each having two input terminals and a single output terminal and a commutator circuit having a first input terminal, a second input terminal connected to one of the input terminals of one of the ''''OR EXCLUSIVE'''' circuits, a control terminal connected to the output terminal of said one ''''OR EXCLUSIVE'''' circuit and to one of the input terminals of the other ''''OR EXCLUSIVE'''' circuit, and an output terminal, said commutator circuit further comprising two transistors of inverse types having collectors, emitters and bases, the latter being connected to said control terminal through equal resistances, and the emitter of one transistor and the collector of the other transistor being connected to the output terminal of the commutator circuit, whereby said commutator circuit is capable of connecting its output terminal to one of its input terminals when a voltage indicating the binary number 1 is applied to said control terminal and of connecting its output terminal to its other input terminal when a voltage indicating the binary number 0 is applied to said control terminal.
 48. A binary adder for two numbers and a carryover represented by means of electrical voltages indicating binary numbers 0 and 1 comprising two logical ''''OR EXCLUSIVE'''' circuits each having two input terminals and a single output terminal, and a commutator circuit having a first input terminal, a second input terminal connected to one of the input terminals of one of the ''''OR EXCLUSIVE'''' circuits, a control terminal connected to the output terminal of said one ''''OR EXCLUSIVE'''' circuit and to one of the input terminals of the other ''''OR EXCLUSIVE'''' circuit, and an output terminal, said commutator circuit being capable of connecting its output terminal to one of its input terminals when a voltage indicating the binary number 1 is applied to said control terminal and of connecting its output terminal to its other input terminal when a voltage indicating the binary number 0 is applied to said control terminal, and a said ''''OR EXCLUSIVE'''' circuit includes a comparator comprising a transistor having a collector, an emitter and a base, means including a first resistor connecting said collector to one terminal of a source of voltage, means including a second resistor connecting said emitter to the other terminal of said source, said resistors being of substantially equal resistance value, an output terminal connected to said collector, and a pair of resistors connected in parallel to said base and each to a separate input terminal of the said ''''OR EXCLUSIVE'''' circuit, the resistors of said pair having substantially equal resistance values which are low in comparison to the resistance values of said first and second resistors. 